The present invention relates generally to the fabrication of integrated circuits, and more particularly to the formation of contacts and/or diffusion regions in an integrated circuit.
Most integrated circuit (IC) manufacturing processes typically include a number of manufacturing steps that can sequentially form, shape or otherwise modify various layers. Typically devices can be formed in a semiconductor substrate having regions doped for varying conductivity. Electrical connections between a substrate and/or various other layers may be accomplished by way of contact structures, including conductive vias.
One concern with the formation of contact structures can be the resulting resistance presented by a contact structure. As contact resistance increases semiconductor device speed can slow down. Because system speeds continue rise, lowering contact resistance continues to be a goal for many integrated circuit manufacturers.
One aspect of a contact structure that may affect contact resistance is contact area. Contact area can be a cross-sectional area of a junction between a contact and another material. For example, an area where a contact makes a connection to a semiconductor substrate can represent a contact area. In addition, an area where a via makes a connection to an underlying (and in some cases overlying) conductive pattern can represent a contact area. In some cases, a manufacturing process may have a minimum contact resistance value. Thus, it is desirable that a contact forming process be capable of meeting a minimum contact resistance value.
Typically, a contact structure may be formed by depositing an insulating layer over an underlying conducting layer. Conducting layers, as but one example, may include a conductor material, a semiconductor material, or some combination thereof. A hole may then be formed through the insulating layer to expose a portion of the underlying conducting layer. A contact material may then be formed in the contact hole that makes electrical contact with the underlying conducting layer. In this way, in many approaches, contact area may be determined by a contact hole formation step.
While a higher contact area is desirable, such a goal may conflict with the competing interest of making an integrated circuit as small as possible. For example, past manufacturing processes have included minimum spacing requirements between a contact hole and other structures. Such minimum spacing requirements can result in a larger device surface area. This can translate directly into a more costly semiconductor device. Thus, larger contact sizes have, in some conventional cases, come at the cost of increased device size.
One way to overcome such contact spacing constraints has been to use xe2x80x9cself-alignedxe2x80x9d contacts. A self-aligned contact may include an underlying structure that includes an insulating spacer (also referred to as a sidewall). A spacer can prevent a contact hole from exposing a corresponding underlying structure. This can enable a contact hole to overlap an adjacent structurexe2x80x94thus overcoming a minimum lateral spacing requirement.
A particular structure that may include a self-aligned contacts is an insulated gate field effect transistor (IGFET), such as a metal-oxide-semiconductor (MOS) FETs. Because transistors currently remain an elementary integrated circuit element, it is desirable to arrive at some way of making contacts to a transistor that can provide increased area, but not significantly increase the overall area of a transistor.
Many transistors can include one or more contacts to an active area. As one particular example, a transistor may include a source and drain regions formed in a substrate. In the case of an IGFET, a gate can be situated between a source and drain that includes spacers. Spacers on a gate may eliminate a minimum spacing requirement between a gate and source and drain regions.
To better understand the formation of certain integrated circuit structures, including contacts structures, a particular conventional self-aligned contact (SAC) approach is set forth in FIGS. 7A-7F. FIGS. 7A-7F set forth a number of side cross-sectional views of a portion of an integrated circuit.
FIG. 7A shows a substrate 700 on which may be formed one or more gate structures 702 of an insulated gate field effect transistor, such as a MOSFET. A substrate 700 many include doped monocrystalline silicon in which diffusion regions may be formed. A substrate 700 may also include isolation structures (not shown). A gate 702 can include a conductive portion 704 that may comprise doped polycrystalline (poly) silicon having a layer of silicide formed thereon. A gate 702 may further include a top insulating layer 706. A top insulating layer may comprise silicon nitride formed by chemical vapor deposition (CVD) techniques.
Referring to FIG. 7B, following the formation of gate structures 702, a spacer insulating layer 708 may be deposited. A spacer insulating layer 708 may comprise silicon nitride formed by CVD techniques.
Referring to FIG. 7C, an etch, such as an anisotropic etch, may remove portions of an insulating layer 708 and form spacers 710. Spacers 710 in combination with a top insulating layer 706 may allow for contacts that are self-aligned with respect to a gate structure 702.
FIG. 7D shows an integrated circuit following the formation of an interlayer dielectric 712. An interlayer dielectric 712 can insulate a substrate 700 and/or a conductive portion 704 from a subsequently formed interconnect pattern. An interlayer dielectric 712 may include borophosphosilicate glass (BPSG) and/or phosphosilicate glass (PSG) and/or undoped silicate glass (USG), to name but a few examples.
An interlayer dielectric 712 may also be planarized. A planarization step may include chemical-mechanical polishing (CMP), as but one example. Following the planarization of an interlayer dielectric 712 a self-aligned contact (SAC) etch mask may be formed. Such an etch mask may include an opening over a desired location for a contact hole. A xe2x80x9ccapxe2x80x9d layer of silicon dioxide 713 can be formed over an interlayer dielectric 712.
Once a SAC etch mask has been formed, a contact hole may be etched through an interlayer dielectric 712 and a cap layer 713 that exposes a portion of a substrate 700. A contact hole etch may include an anisotropic reactive ion etch (RIE), as but one example. A semiconductor device following the formation of a contact hole 714 is shown in FIG. 7E.
Referring now to FIG. 7F, a conductive material 716 may be formed in a contact hole 714 that may provide a conductive path to a substrate 700. As but one example, a metal such as tungsten may be deposited into a contact hole 714. Following such a deposition, a planarization step, that may include CMP, can be performed. A semiconductor device following the deposition and planarization of a conductive material 716 is show in FIG. 7F.
FIG. 7F illustrates how spacers 710 may reduce available substrate area for a contact. In particular, FIG. 7F shows a number of measurements, including a contact material critical dimension (CD) measurement 718, shoulder loss measurements 720, and a contact area measurement 722. A contact material CD 718 may represent the smallest possible, or smallest desirable feature size for a conductive material 716 in a contact structure. Shoulder loss measurements 720 may represent a thickness of an insulating spacer that may encroach on a contact area. Contact area measurement 722 shows a resulting contact area taken by subtracting shoulder loss 720 from a contact material CD 718. Thus, increases in shoulder loss 720 can translate into decreased contact area, and hence higher contact resistance.
In addition to contact resistance and contact spacing requirements, another concern with integrated circuits can be the formation of doped regions in a substrate. For example, the formation of source and drain regions can affect the performance of a transistor. As transistor channel lengths have continued to shrink, the doping profiles of source and drain regions has increasingly impacted performance.
Source and drain regions are typically formed by forming oppositely doped regions in a semiconductor substrate. In most structures, a sharper doping profile can result in less leakage. Conversely, a more gradual doping profile may result in increased leakage. It is therefore desirable to form source and drain regions with sharper profiles if low leakage is a goal.
An increasing concern with small transistors, such as MOSFETs, has been xe2x80x9cshort channelxe2x80x9d effects. Short channel can include hot-carrier effects that may result in unstable transistor operation and/or reduce transistor reliability. One way to reduce hot carrier effects is with lightly doped drain (LDD) regions. An LDD structure can typically include a lightly doped region between a source/drain and a corresponding channel.
One conventional approach to forming LDD regions may include an LDD ion implantation step prior to the formation of spacers. A xe2x80x9cdeepxe2x80x9d or higher concentration ion implantation may then occur after the formation of spacers. This may produce an LDD region between a higher doped source/drain region and a corresponding transistor gate.
While conventional LDD regions may reduce short channel effects, such approaches may not provide sufficient distance between a more highly doped region and a transistor channel. Additional distance between a more highly doped source/drain region may be achieved with a spacer of increased thickness. However, as noted above, increasing spacer thickness can encroach on overall contact area. The converse can be true as well. Increased contact area may be achieved by reducing spacer thickness, but at the cost of increased transistor leakage.
It would be desirable to arrive at some way of providing reduced contact resistance without necessarily incurring the adverse effects of arising out of source/drain regions that formed too close to a transistor channel.
U.S. Pat. No. 5,763,312 issued to Jeng et al. and U.S. Pat. No. 5,899,722 issued to Huang teach arrangements in which a first spacer of silicon nitride is formed on gate conductor stacks. A silicon dioxide spacer is then formed on the silicon nitride spacer. A blanket dielectric layer can then formed over the gate structures. A self-aligned contact hole is etched through the blanket dielectric layer. The self-aligned contact hole etch removes the silicon dioxide spacer. A drawback to such an arrangement is that a single etch recipe may not be optimized for removal of both a blanket dielectric layer and a second spacer. Thus, underetch may occur, in which case residual second spacer can remain, or overetch may occur, in which case the substrate may be undesirably etched. If a second spacer is not removed a contact area can be smaller.
U.S. Pat. No. 5,846,857 issued to Ju discloses a process for optimizing N- and P-channel transistors that includes forming a first spacer of silicon dioxide on a transistor gate. A second spacer of silicon nitride is then formed on the first spacer spacer. The second spacer may then be removed. Ju does not appear to provide teachings on contact formation.
U.S. Pat. No. 5,851,866 issued to Son discloses NMOS and PMOS transistor gates having first spacers formed from phosphosilicate glass (PSG) and second spacers formed on the first spacers. The second spacers can be formed from silicon dioxide. Son does not appear to shown the removal of the second spacer.
U.S. Pat. No. 5,866,460 issued to Akram et al. shows a field effect transistor that includes a multiple implant lightly doped drain. Implants may be performed following the formation of a number of thin gate spacers. Alternatively, a thick spacer may be formed. Portions of the thick spacer may be removed with multiple etch steps, each accompanied by an implantation step. Akram et al. does not appear to disclose spacer spacers of different materials.
The various disclosed embodiments set forth methods of forming contacts. Particular embodiments disclose methods of forming self-aligned contacts to source and drain regions of a transistor having low leakage characteristics.
According to one embodiment, diffusion regions may be formed in a semiconductor device with a gate structure and first and second spacers as a mask. A second spacer may then be removed. An interlayer dielectric may then be formed over a gate structure and remaining first spacer. A contact hole may then be etched through an interlayer dielectric that can be self-aligned with respect to a gate structure. Such an approach may form transistors having source/drain regions spaced from a channel by a thickness of two spacers and a contact hole separated from a gate structure by a single spacer. Further, removing a second spacer prior to a self-aligned contact etch may allow for a contact etch to be tailored to an interlayer dielectric material. Removal of a second spacer can increase contact area.
According to one aspect of the embodiments, a first spacer may comprise silicon nitride while a second spacer may comprise silicon dioxide.
According to another aspect of the embodiments, a second spacer may be removed with a substantially isotropic etch. An isotropic etch can be a wet chemical etch.
According to another aspect of the embodiments, an interlayer dielectric may comprise high density plasma (HDP) phosphosilicate glass (PSG). A contact etch may be highly selective between HDP PSG and a silicon nitride first spacer.
According to another aspect of the embodiments, other diffusion regions may be formed in a semiconductor device with a gate structure as a mask prior to the formation of first and second spacers.
According to another aspect of the embodiments, a contact may be formed in an etched contact hole that includes a liner layer. A liner layer may form a contact diffusion barrier at a substrate and/or provide adhesion of a subsequent contact material to a liner.